1. Field of the Invention
This invention relates to computer system input/output and, more particularly, to transaction reordering within a peripheral interface circuit.
2. Description of the Related Art
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. The I/O devices may be coupled to the processors through an I/O bridge which manages the transfer of information between a peripheral bus connected to the I/O devices and a shared bus connected to the processors. Additionally, the I/O bridge may manage the transfer of information between a system memory and the I/O devices or the system memory and the processors.
Unfortunately, many bus systems suffer from several drawbacks. For example, multiple devices attached to a bus may present a relatively large electrical capacitance to devices driving signals on the bus. In addition, the multiple attach points on a shared bus produce signal reflections at high signal frequencies which reduce signal integrity. As a result, signal frequencies on the bus are generally kept relatively low in order to maintain signal integrity at an acceptable level. The relatively low signal frequencies reduce signal bandwidth, limiting the performance of devices attached to the bus.
Lack of scalability to larger numbers of devices is another disadvantage of shared bus systems. The available bandwidth of a shared bus is substantially fixed (and may decrease if adding additional devices causes a reduction in signal frequencies upon the bus). Once the bandwidth requirements of the devices attached to the bus (either directly or indirectly) exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting access to the bus, and overall performance of the computer system including the shared bus will most likely be reduced. An example of a shared bus used by I/O devices is a peripheral component interconnect (PCI) bus.
Many I/O bridging devices use a buffering mechanism to buffer a number of pending transactions from the PCI bus to a final destination bus. However buffering may introduce stalls on the PCI bus. Stalls may be caused when a series of transactions are buffered in a queue and awaiting transmission to a destination bus and a stall occurs on the destination bus, which stops forward progress. Then a transaction that will allow those waiting transactions to complete arrives at the queue and is stored behind the other transactions. To break the stall, the transactions in the queue must somehow be reordered to allow the newly arrived transaction to be transmitted ahead of the pending transactions. Thus, to prevent scenarios such as this, the PCI bus specification prescribes a set of reordering rules that govern the handling and ordering of PCI bus transactions.
To overcome some of the drawbacks of a shared bus, some computers systems may use packet-based communications between devices or nodes. In such systems, nodes may communicate with each other by exchanging packets of information. In general, a xe2x80x9cnodexe2x80x9d is a device which is capable of participating in transactions upon an interconnect. For example, the interconnect may be packet-based, and the node may be configured to receive and transmit packets. Generally speaking, a xe2x80x9cpacketxe2x80x9d is a communication between two nodes: an initiating or xe2x80x9csourcexe2x80x9d node which transmits the packet and a destination or xe2x80x9ctargetxe2x80x9d node which receives the packet. When a packet reaches the target node, the target node accepts the information conveyed by the packet and processes the information internally. A node located on a communication path between the source and target nodes may relay or forward the packet from the source node to the target node.
Additionally, there are systems that use a combination of packet-based communications and bus-based communications. For example, a system may connect to a PCI bus. The PCI bus may be connected to a packet bus interface that may then translate PCI bus transactions into packet transactions for transmission on a packet bus. The interface may communicate with a host bridge associated with one of the processors or in some cases to another peripheral device.
When PCI devices initiate the transactions, the packet-based transactions may be constrained by the same ordering rules as set forth in the PCI Local Bus specification. The same may be true for packet transactions destined for the PCI bus. These ordering rules are still observed in the packet-based transactions since transaction stalls that may occur at a packet bus interface may cause a deadlock at that packet bus interface. This deadlock may cause further stalls back into the packet bus fabric.
Commands destined for a target device on a peripheral bus may be responses to requests originally made by the target device. Depending on the I/O configuration, number of nodes, etc. it is possible that the responses may be received by a packet bus interface in a different order than the target device sent the original request. Depending on the ordering rules imposed on the I/O node by the target peripheral bus, the responses may be required to be reordered prior to being sent to the target device. Thus, an apparatus for reordering transactions within a peripheral interface may be desired.
Various embodiments of an apparatus for reordering packet transactions within a peripheral interface circuit are disclosed. In one embodiment, an apparatus for reordering packet transactions in a peripheral interface circuit includes a source tagging unit and a control unit coupled to the source tagging unit. The source tagging unit may generate a plurality of tag values such that each of the plurality of tag values corresponds to one of a plurality of packet commands. The control unit may include a first storage unit and a second storage unit. The second storage unit may be coupled to the first storage unit. Further, the first storage unit may include a first plurality of locations each corresponding to one of the plurality of tag values. Each of the first plurality of locations may provide an indication of whether a given tag value corresponds to a first packet command in a given data stream. The second storage unit may include a second plurality of locations each corresponding to one of the plurality of tag values. A first given location of the second plurality of locations corresponds to a tag value indicated by the first storage unit as corresponding to the first packet command. The first given location may store a tag value of a second packet command in the given data stream.
In a particular implementation, the first packet command may precede the second packet command in the given data stream. Further, the tag value contained within the first given location may be an index to a second given location of the second plurality of locations. The second given location may store a tag value of a third packet command in the given data stream. The second packet command precedes the third packet command in the given data stream.
In another specific implementation, the control unit may further include a third storage unit coupled to the second storage unit and may include a third plurality of locations each corresponding to one of the plurality of tag values. Each of the third plurality of locations may provide an indication of whether a given tag value corresponds to a last packet command in the given data stream.